I'm curious, and knowing nothing about the determinants of power draw and node process: wouldn't a "nearer-to-cutting-edge" fab process, though, still end up producing processors that draw even less energy? Or has that not been a goal of recent semiconductor progress?
The silicon that drives IO pins & oscillator(s) requires some physical size (for one, due to ESD protection reasons), and requires X amount of power.
A complex, modern cpu can consume many times that, so cutting edge process is useful to minimize overall power use.
With small/simple parts like a uC, not so much. So the cost/part, other considerations, and whatever vendor or silicon process provides that, is what matters.
Here, power savings come from sleep modes, disabled peripherals & (maybe) reduced or even stopped clocks. Not so much reduced feature sizes in the IC.
