Interesting, that makes sense, but my point still stands: all 8 of those devices fall down 4-8x in speed at some point, meaning for sequential transfers speed falls off and can handle 4-8x less lanes
The performance drop due to SLC caching only applies to writes. Sequential reads (and often, even random reads at sufficiently high queue depth) will still more or less saturate the PCIe link. Most workloads and use cases read a lot more data than they write.
