An interesting revelation here is that, although ENIAC was not originally conceived as a stored program computer, it was quite early converted to one. They repurposed a lookup table intended to calculate functions to store instructions instead. Many of the well-known ENIAC calculations, such as Monte Carlo simulations, were programmed in this mode.
Hoare's undergraduate degree from Oxford was in Literae Humaniores, nicknamed Greats - ancient Rome, ancient Greece, Latin, Ancient Greek, and philosophy. In the US, this course of study is usually called "Classics".
According to Wikipedia, "It is an archetypal humanities course."
Hastings affected the wider politics of Europe, not just England. For centuries before Hastings, England had been involved with Scandinavia, especially Denmark and Norway. After Hastings it was totally entangled with France, pretty much forever.
To me, it's plausible one might be able to make a similarly small RISCY-V02 on a 70s Rubylith NMOS process with dynamic logic, using pass transistors and tristate busses, all laid out by hand. But I definitely can't do that, and even if I could, I'd have no way to validate that it actually works.
Best I could do was an A/B comparison on a modern process: a clean Verilog model of RISCY-V02, and a clean Verilog model of a 6502, both run through a modern synthesis process for TinyTapeout. Same slosh, inoptimality, and behavior. So, this is a static CMOS design, like the 65C02, on a modernish process node. That being said, the 65C02 had around 11K transistors, so we're not too far off.
This establishes horseshoes and hand grenades plausibility, but basically nothing else. But, it's also a pretty nifty CPU design if I do say so myself!
Thanks, I see. In your README you do briefly mention static vs dynamic, NMOS vs CMOS, and 6502 vs 65C02 but I didn't appreciate those could make a 3x difference in the transistor count.
I agree it's a nice CPU design, and the whole project is quite impressive. Will Tiny Tapeout make you an actual chip that you can run?
I'm curious about how you used Claude. Is the CPU design itself completely handmade, or did Claude fill in some details? Did you use Claude for both the Verilog code and the Python emulator and test code? Did you provide Claude
with some of your own hand-written code to demonstrate the style you wanted and get it started?
TT will either make me a chip I can run, a chip I can run with some workarounds, or garbage. Only time will tell!
As for Claude, honestly, as a partner. We bounced ideas off each other, while I provided overall direction for the project. It was finishing up a design I had started and aborted last year, but we did build this from scratch. I had some good ideas, Claude had some good ideas, but Claude did almost all of the actual grunt work. Looking back, Claude's tactical decisionmaking was often better than mine, but my strategic decisionmaking was far superior. I would also occasionally have to interject when it was "freaking out" and offer a sounding board to help it solve whatever problem it was working through.
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