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All the updates (so far…) have added features that I actually like. Things like Apple Music integration and even safety things like cross-traffic alerts when reversing.

Even today my wife left her phone on the charge pad and the car beeped as we walked away to alert us - a feature that didn’t exist when we first got it.

Enshittification may come, but maybe there will be an Apple-like benevolent dictator that keeps it mostly clean.

Edit: I should say that I will never trust any “self-driving” at all based on cameras alone. It can’t even do Autopilot without me intervening on most trips.


What if I want to talk to Hairy Boris but I’m getting scammed by some blonde bombshell pretending to be him? I shudder at the thought.

There must be something wrong with quite a lot of hardware then. My windows laptop at work took > 20 seconds to open the right-click menu on the desktop.

During the wait the entire desktop background went black along with the icons then it came back. I was actually trying to get to a setting to set the background to a fixed colour instead of an image in the hope of speeding the machine up.

From a UX experience there was zero indication that it was trying to do anything during this time.


Given the list of alternatives you provided I’m inclined to disagree with you.

I'm developing on a $270 refurbished Dell, which has an i7 and 16 gigs of RAM. The Apple processor might be competitive, but the rest of the machine is not. 600 dollars is fine and not unreasonable, but there is certainly an Apple tax.

Imagine what humanity could achieve if we worked together. If robots/AI work out and we do have 100% spare time then you’d hope there would be more of this sort of thing.

Such a shame that it’ll probably just mean more inequality, at least in the short term.


> If robots/AI work out and we do have 100% spare time then you’d hope there would be more of this sort of thing.

If robots/AI work out we will need to use 100% of our spare time to work what few jobs are still available to humans so we can earn enough money to pay rent.


No, that's an example of robots/AI not working out. Yes, this means that "making robots/AI work out" is a political and economic problem, not just a technical one.

It's really unfortunate that the people who run the biggest AI companies don't share your definition of success.

Yeah, definitely not taking the risk with personal travel at all - especially travelling with young children. Sorry but Disneyland will have to wait until the next election.

Work would have to promise to pay me even if a hired goon locked me up for a few months before I’d consider a business trip.


That shouldn’t make sense. It’s not like the ECC info is stored in additional bits separate from the data, it’s built in with the data so you can’t “ignore” it. Hmm, off to read the paper.

The ECC information is stored in separate DRAM devices on the DIMM. This is responsible for some of the increased cost of DIMMs with ECC at a given size. When marketed the extra memory for ECC are typically not included in the size for DIMMs so a 32GB DIMM with and without ECC will have differing numbers of total DRAM devices.

There's a pretty good set of diagrams and descriptions of the faults in this paper https://dl.acm.org/doi/10.1145/3725843.3756089.

Also to the parent: there's an updated public paper on DDR4 era fault observations https://ieeexplore.ieee.org/document/10071066


I think you responded to the wrong person, unless you think I was implying that the extra bits needed for ECC didn’t need extra space at all? I wasn’t suggesting that - just that they aren’t like a checksum that is stored elsewhere or something that can be ignored - the whole 72 bits are needed to decode the 64 bits of data and the 64 bits of data cannot be read independently.

If we're talking about standard server RDIMMs with ECC (or the prosumer stuff) the CPU visible ECC (excluding DDR5's on-die ECC) is typically implemented as a sideband value you could ignore if you disabled the correction logic.

I suppose what winds up where is up to the memory controller but (for DDR5) in each BL16 transaction beat you're usually getting 32 bits of data value and 8 bits of ECC (per sub channel). Those ECC bits are usually called check bits CB[7:0] and they accompany the data bits DQ[31:0] .

If you're talking about transactions for LPDDR things are a bit different there, though as that has to be transmitted inband with your data


We are talking about errors happening in user space applications with ECC operating normally and what the application ultimately sees.

My point is that when writing an app you wouldn’t be able to “not use” ECC accidentally or easily if it’s there. It’s just seamless. I’m not talking about special test modes or accessing stuff differently on purpose.

Interesting that DDR5 is different than DDR4. 8 bits for 32 is doubling of 8 for 64 so it must have been warranted.


I fully agree with you ! Neither soft nor hard memory errors, nothing… but but flips ,and reproducible at that.

We scanned all our machines following this ( a few thousand servers ) and found out that ram issues were actually quite common, as said in the paper.


That would look good on a headstone.


That was probably fine for portraying Listers character to be fair.


I just picked up a NAS - a ugreen dxp2800 - for £300. It has 2x nvme slots and 2x 3.5 bays. It’s x86 so if you don’t like the ugreen os you can change it.

It runs docker (supports docker compose) and vms and has the usual raid stuff.

They also do an arm version for half the price but I wanted the intel gpu for transcoding.


Does it take ECC RAM?


It doesn’t - I’ve had a quick look and I don’t think even their top model does.


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