It definitely will be a cool chip to mess with but is not yet complete. At the workshop, Wei Song presented our latest work on adding trace debug features (which will be properly introduced on the blog soon). We expect to be RTL complete early next year and to tape out an initial test chip later in 2017.
Do you have any initial specs that you see on the horizon (whatever you're targeting)?
Some things I'd like to know about are temperature requirements, power requirements, IO, if there is an on chip ADC & DAC, clock specs with temp requirements, and radiation hardness.
Getting even preliminary information on that stuff would be amazing!
Target: 28nm, 4x 1GHz+ application cores, ~8 minion cores (see http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-...), tagged memory, USB, LPDDR3. For more detailed specs, that's going to depend on confirming those details and the package design.
Our aim is open source to the RTL. Open analog IP (e.g. the DDR PHY and USB PHY) is a much more difficult proposition - it's process specific, and reliant on NDAed/trade secret details of the particular process making redistribution difficult. Therefore, we will use existing commercial PHYs, and it may make sense initially to use the standard proprietary controller it has been verified against. Over the long term, as I say, we'd like all RTL to be open but you've got to start somewhere. I think there's a parallel to the early days of GNU where they worked on replacing UNIX components piece by piece. It would be great if we could share the place+routed design at zero cost to anyone with the appropriate agreement with the fab.
We currently store tags in a separate region of physical memory, though you could imagine "borrowing" ECC bits. A tag cache (which due to the small size of tags can have a large reach) reduces the number of instances where you might have read or write multiplication. We're about to start work on further optimisations on this.
