Placement is usually as important as routing, if not more so. At the same time, the act of thinking carefully about placement will often making routing easier. I try to take a holistic view -- I don't see routing as grunt work, or as an unnecessary chore, but as part of the design process.
On a long-enough timeline, ML tools will become a natural fit for placement and routing. It is a rather dumb thing for humans to have to deal with, at the end of the day, but the existing tools are just not good enough to take over the job. At least not the tools that most of us have access to.
Unless ML tools know which nets have how much current/voltages on them, as well as which ones are sensitive to noise... as well as rise/fall times of each pin, its a hopeless job.
Lets say you have a trace that's 4mm wide that skips across a slot in the ground-plane. Is this good or bad?
1. Why is it 4mm? Is this a high-current line / power line of some kind? A crude power-plane that's just oversized for a trace? Is this a switching regulator with a bit of switching noise? Or is it a "quiet" power line, like a battery or LDO-line?
2. Is this trace actually ground? And the 4mm is to "jump" across the gnd-slot to provide a controlled return-path for some other line? What is the relationship of this trace vs another trace?
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If its a fat line on a switching power supply with a ton of current, maybe its a bad idea. If its a fat gnd, maybe its a good idea. Its all contextual. Its not very clear how a hypothetical ML tool would figure out this context, outside of like learning to read data-sheets and/or the EE writing down the purpose (very precisely) on each net... which probably is slower than just routing the trace manually to begin with.
Are you going to put the source-code of your programs in there too? I'm not sure how a ML model would ever know that... say... Pin A5 is a rarely-changing GPIO that's effectively DC. Or that Pin-B6 is configured as an analog-DAC in this particular application (and therefore slowly changing).
Or hell, that PinC1 is an input vs output.
Modern chips have very flexible pins. Many microprocessors (and MCUs) can configure any pin to be input, output, tri-state output, pull-up output, or pull-down output, for example, with different properties in each state. Some pins can be analog (on-board op-amps), others can be digital and high frequency, still others can be digital but rarely-changing / effectively DC for the lifetime of the application.
In general, you can organize specifications and verification information in a way that can be consumed by other programs for the purpose of synthesizing designs or generating tests or whatever. At that point, an optimizer could do a a decent job of routing. I guess ML could add value somewhere in that process to handle some unstructured aspect.
On a long-enough timeline, ML tools will become a natural fit for placement and routing. It is a rather dumb thing for humans to have to deal with, at the end of the day, but the existing tools are just not good enough to take over the job. At least not the tools that most of us have access to.