Each chiplet comes with its own tool chain. The FPGA has a full RTL2BITS tool chain, the CPU is supported by standard RISC-V tools, and the ML chiplet will have a typical ML programming flow. The full system parallel heterogeneous programming challenge is something the whole industry is grappling with. It's an unsolved problem. DARPA started a program on this topic in 2020 called PAPPA.
The manycore emulation demo kind of hints at where we are going...more information to follow in the next few months.
The manycore emulation demo kind of hints at where we are going...more information to follow in the next few months.
https://www.zeroasic.com/emulation