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Silicon lattice constant (roughly the distance between atoms) is 0.56nm. The 5nm process will have 10 atom transistors. It's hard to imagine a traditional process smaller than that. That means that the end if Moore's law is near.


I think quantum computing with quantum states in atoms being transistor states will be final progression of Moore's Law. But we are definitely feeling the effects of the end right now. I think it was Michio Kaku who said that we have about 50 years left until Moore's Law is officially done ushering in the collapse of the industry and global economy.


>I think it was Michio Kaku who said that we have about 50 years left until Moore's Law is officially done ushering in the collapse of the industry and global economy.

Not even sure what he means. The efficiency of processors, especially beyond a certain point, hardly makes any difference to the "global economy".

Heck, there are even notable economists saying that the effect of the whole "www" on the economy wasn't that special compared to things like the first telecommunications, road and planes.

It's difficult to see when ones lives and breath in the IT industry echo chamber, but, you know, diminishing returns.

The fact that despite 50 years of Moore's law we didn't have anything like a 8,589,934,592 [1] times larger global economy, actually not even a 100x larger, should be enough proof that the Moore's law doesn't have a strong influence on it...

[1] 2^((50*12)/18).


The effect of the silicon computers was huge however (office productivity, industry automation, embedded systems, numerical modeling of analog systems such as biotech, airfoils, etc)


To many experts back in the day it was hard to imagine a traditional process below 100nm.


i am not an expert, but this is an elementary physics knowledge.


LOL, yep, they said something similar: "You have to break laws of physics to get under 100nm". When you reach a single atom limit, why can't you start building vertical structures? Moore's law specifies the number of transistors per area, it says nothing about the height of that area. Specifically, you're not restricted to a single layer.


Because:

1. going from 2D to 3D is a one time improvement, not a continuous law that runs for 30 years: at some future point, say a 5nm process becomes 3D, and the number of transistors jumps from N^2 to N^3. That's a single time change.

2. making single atom conventional logic gates is physically impossible: it will have quantum effects and thus will behave like a quantum computer. To make a classical (non-quantum) logic gate, you need at least 8-10 atoms (and that's pushing it).


No, going from 1xN^2 to 2xN^2 to 3xN^2 and each further stacked layer from there on is still going to be a very major challenge (getting rid of heat being a very major physical challenge for a start). We're already 32 x N^2 for flash packages, but with stacked dies. For flash heat is much easier to manage as only a small part of the die is active at any one time. Stacking memory on top of a cpu core is also common practice in mobile SoCs (though still mostly package-on-package). Going to N^3 from todays M x N^2 is squarely (cubedly? ;)) in the realm of science fiction, there's a lot of space for improvement here.




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