Interestingly if you are doing a standard height four layer stack up with something like signal-power-ground-signal your stripline is much closer to the plane and default trace widths have a natural impedance much closer to what you want. On two layer even if most of one side is a ground plane the distance from trace to plane leads to impedance much further out of spec. I haven't had to do any sort of impedance controlled traces yet luckily on a two layer where standard 1.6mm PCBs mean something crazy like 3mm trace widths to hit 50 ohms characteristic impedance at ~100-150MHz.
I think about 150mm is the furthest I've routed non-terminated 100MHz uSD lines and I've been lucky enough so far to get away with the only real design goal being all trace lengths within +/- 5% of the clock line, even with the trace lines having a couple hundred ohms of Z when the spec calls for 50. I do wonder things like if my error rate went from once per 20 years to once per 5 years type of thing. I'm also guessing the error rate follows some sort of inverse S-curve of probability.
I think about 150mm is the furthest I've routed non-terminated 100MHz uSD lines and I've been lucky enough so far to get away with the only real design goal being all trace lengths within +/- 5% of the clock line, even with the trace lines having a couple hundred ohms of Z when the spec calls for 50. I do wonder things like if my error rate went from once per 20 years to once per 5 years type of thing. I'm also guessing the error rate follows some sort of inverse S-curve of probability.